HiPar20 is designed to showcase new studies, approaches, and cutting-edge ideas on hierarchical parallelism for extreme-scale computing. Our goal is to highlight not just success stories but also discuss drawbacks and challenges.

We welcome papers and talks from the HPC community addressing the use of emerging architectures — focusing particularly on those characterized by fewer but more powerful nodes as well as systems with hierarchical networks, where the hierarchy is not just characterized by performance metrics, but tiered communication semantics. Specifically, the emphasis is on the design, implementation, and application of programming models for multi-level parallelism, including abstractions for hierarchical memory access, heterogeneity, multi-threading, vectorization, and energy efficiency, as well as scalability and performance studies thereof.

Of particular interest are models addressing these concerns portably: providing ease of programming and maintaining performance in the presence of varied accelerators, hardware configurations, and execution models. Studies that explore the merits of specific approaches to addressing these concerns, such as generic programming or domain specific languages, are also in scope.

The workshop is not limited to the traditional HPC software community. As one example, another key topic is the use of hierarchical parallelism in dealing with the challenges arising in machine learning, due to the growing importance of this field, the large scale of systems tackled in that area, and the increasing interest at SC.

Submissions are encouraged in, but not limited to the following areas:

• Hierarchical work scheduling and execution;
• Hardware, software and algorithmic advances for efficient use of memory hierarchies, multi-threading and vectorization;
• Efficient use of nested parallelism, for example CUDA dynamic parallelism, for large scale simulations;
• Programming heterogeneous nodes;
• Leading edge programming models, for example fully distributed task-based models and hybrid MPI+X, with X representing shared memory parallelism via threads, vectorization, tasking or parallel loop constructs;
• Implementations of algorithms that are natural fits for nested work (for example approaches that use recursion);
• Challenges and successes in managing computing hierarchies;
• Examples demonstrating effective use of the combination of inter-node and intra-node parallelism;
• Novel approaches leveraging asynchronous execution to maximize efficiency;
• Challenges and successes of porting of existing applications to many-core and heterogeneous platforms;
• Recent developments in compiler optimizations for emerging architectures;
• Applications from emerging AI fields, for example deep learning and extreme-scale data analytics.

Submissions are solicited in the following categories:

(a) Regular research papers:

Intended for submissions describing original work and ideas that have not appeared in another conference or journal, and are not currently under review for any other conference or journal.
Regular papers must be at least (6) and not exceed (10) letter size pages (U.S. letter – 8.5″x11″).
Accepted regular papers will be published in the workshop proceedings in cooperation with IEEE TCHPC (pending acceptance).

(b) Short papers:

Intended for submissions presenting novel, interesting ideas or preliminary results that will be formally submitted elsewhere.
Short papers must not exceed four (4) pages.
Short papers will NOT be included in the proceedings.
 

Please note that:

The page limits above only apply to the core text, content-related appendices, and figures.
References and reproducibility appendix do not count against the page limit.

When deciding between submissions with comparable evaluations, priority will be given to those with higher quality of presentation and whose focus relates more directly to the workshop themes.

Papers must be submitted at https://submissions.supercomputing.org and must follow the IEEE format: https://www.ieee.org/conferences/publishing/templates.html

HiPar20 follows the SC20 reproducibility and transparency initiative:
https://sc20.supercomputing.org/submit/transparency-reproducibility-initiative

HiPar20 requires all submission to include an Artifact Description (AD) Appendix.
The Artifact Evaluation (AE) remains optional.

We also encourage authors to follow the transparency initiative for two reasons:
(a) it helps the authors themselves with the actual writing and structuring of the paper to express the research process;
(b) it helps readers understand the thinking process used by the authors to plan, obtain and explain their results.