Friday, 18th November 2022
In cooperation with:
Held in conjunction with:
Industrial competition, the explosion of AI and machine learning, and the computational needs of leading-edge scientific research are driving rapid changes and advancements in High Performance Computing (HPC). Computational nodes are becoming increasingly more powerful, featuring a large number of physical cores in multiple sockets and accelerators.
This increases the overall complexity, due to complex architectures (e.g., memory hierarchies and tens of compute elements), novel accelerator designs, and energy constraints. Hierarchical parallelism is an approach that is gaining momentum in HPC: it embraces the intrinsic complexity of current and future HPC systems, rather than avoiding it, by exploiting parallelism at all levels: compute, memory and network.
Hierarchical parallelism is the focus of this workshop. We aim at bringing together hardware, application and software practitioners proposing new strategies to fully exploit computational hierarchies, and examples to illustrate their benefits for extreme scale computing.
WORKSHOP PROGRAM
8.30AM – 8.40am (CST)
8.40AM – 9.40am / INvited speaker – SLIDES
Speaker: Damien Lebrun-Grandie (Scientist, Oak Ridge National Labs, USA)
9.40AM – 10.00am / PAPER 1 – SLIDES
Authors: Mathialakan Thavappiragasm (Oak Ridge National Lab., USA), Vivek Kale (Brookhaven National Lab., USA)
10.00AM – 10.30am
10.30AM – 10.50AM / PAPER 2
Authors: Mohit Kumar, Preeti Malakar (Indian Institute of Technology Kanpur)
10.50AM – 11.10AM / PAPER 3 – SLIDES
Authors: Ye Luo (Argonne National Lab., USA), Peter Doak, Paul Kent (Oak Ridge National Lab., USA)
11.10AM – 11.30AM / PAPER 4 – SLIDES
Authors: Ari Rasch, Richard Schulze, Sergei Gorlatch (University of Muenster, Germany)
11.30AM – 11.50AM / PAPER 5 – SLIDES
Authors: Wenqing Peng, Evgenij Belikov (EPCC, UK)
11.50AM – 12.00PM (CST)
WORKSHOP DETAILS
HiPar22 is designed to showcase new studies, approaches, and cutting-edge ideas on hierarchical parallelism for extreme-scale computing. Our goal is to highlight not just success stories but also discuss drawbacks and challenges.
We welcome contributions from the HPC community addressing the use of emerging architectures — focusing particularly on those characterized by fewer but more powerful nodes as well as systems with hierarchical networks, where the hierarchy is not just characterized by performance metrics, but tiered communication semantics. Specifically, the emphasis is on the design, implementation, and application of programming models for multi-level parallelism, including abstractions for hierarchical memory access, heterogeneity, multi-threading, vectorization, and energy efficiency, as well as scalability and performance studies thereof.
Of particular interest are models addressing these concerns portably: providing ease of programming and maintaining performance in the presence of varied accelerators, hardware configurations, and execution models. Studies that explore the merits of specific approaches to addressing these concerns, such as generic programming or domain specific languages, are also in scope.
The workshop is not limited to the traditional HPC software community. As one example, another key topic is the use of hierarchical parallelism in dealing with the challenges arising in machine learning, due to the growing importance of this field, the large scale of systems tackled in that area, and the increasing interest at SC.
Submissions are encouraged in, but not limited to the following areas:
Papers submissions are solicited in the following categories:
(a) Research papers:
Intended to describe original work and ideas that have not appeared in another conference or journal, and are not currently under review for any other conference or journal.
Regular papers must be at least (4) and not exceed (10) letter size pages (U.S. letter – 8.5″x11″).
Accepted regular papers will be published in the workshop proceedings in cooperation with IEEE Computer Society.
(b) Highlight talks/ideas:
Intended for material that is not mature enough for a paper, to present novel, interesting ideas
or preliminary results that will be formally submitted elsewhere.
Submissions must not exceed (2) letter size pages (U.S. letter – 8.5″x11″).
These will NOT be included in the proceedings but will be part of the HiPar program.
Please note:
Papers must follow the IEEE format: https://www.ieee.org/conferences/publishing/templates.html.
The page limits above only apply to the core text, content-related appendices, and figures.
References and reproducibility appendix do not count against the page limit.
When deciding between submissions with comparable evaluations, priority will be given to those with higher quality of presentation and whose focus relates more directly to the workshop themes.
Papers must be submitted at https://submissions.supercomputing.org
HiPar22 follows the SC22 reproducibility and transparency initiative:
https://sc22.supercomputing.org/submit/reproducibility-initiative
HiPar22 requires all submission to include an Artifact Description (AD) Appendix.
The Artifact Evaluation (AE) remains optional.
We also encourage authors to follow the transparency initiative for two reasons:
(a) it helps the authors themselves with the actual writing and structuring of the paper to express the research process;
(b) it helps readers understand the thinking process used by the authors to plan, obtain and explain their results.
Meta
Lawrence Livermore National Lab
Sandia National Labs
NVIDIA
Cineca
Univ. of Bristol
BSC
ZIH Dresden
NVIDIA
Intel
NVIDIA
Oak Ridge National Labs
CSCS
NexGen Analytics
Shanghai J.Tong Univ.
AMD
Meta
Univ. of Trento
NexGen Analytics
In cooperation with:
In cooperation with: